Full metadata record
DC pole | Hodnota | Jazyk |
---|---|---|
dc.contributor.author | Raabe, Andreas | |
dc.contributor.author | Hochgürtel, Stefan | |
dc.contributor.author | Anlauf, Joachim K. | |
dc.contributor.author | Zachmann, Gabriel | |
dc.contributor.editor | Skala, Václav | |
dc.date.accessioned | 2013-02-27T09:27:16Z | |
dc.date.available | 2013-02-27T09:27:16Z | |
dc.date.issued | 2006 | |
dc.identifier.citation | Journal of WSCG. 2006, vol. 14, no. 1-3, p. 17-24. | en |
dc.identifier.isbn | 80-86943-09-7 | |
dc.identifier.issn | 1213-6972 (hardcopy) | |
dc.identifier.issn | 1213-6964 (online) | |
dc.identifier.issn | 1213-6980 (CD-ROM) | |
dc.identifier.uri | http://wscg.zcu.cz/wscg2007/Papers_2007/journal/!WSCG2007_Journal_Final.zip | |
dc.identifier.uri | http://hdl.handle.net/11025/1356 | |
dc.description.abstract | A novel approach for highly space-efficient hardware-accelerated collision detection is presented. This paper focuses on the architecture to traverse bounding volume hierarchies in hardware. It is based on a novel algorithm for testing discretely oriented polytopes (DOPs) for overlap, utilizing only fixed-point (i.e., integer) arithmetic. We derive a bound on the deviation from the mathematically correct result and give formal proof that no false negatives are produced. Simulation results show that real-time collision detection of complex objects at rates required by force-feedback and physicallybased simulations can be obtained. In addition, synthesis results prove the architecture to be highly space efficient. We compare our FPGA-optimized design with a fully parallelized ASIC-targeted architecture and a software implementation. | en |
dc.format | 8 s. | cs |
dc.format.mimetype | application/pdf | |
dc.language.iso | en | en |
dc.publisher | Václav Skala - UNION Agency | cs |
dc.relation.ispartofseries | Journal of WSCG | en |
dc.rights | © Václav Skala - UNION Agency | cs |
dc.subject | hardwarově akcelerovaná detekce kolizí | cs |
dc.subject | grafické objekty | cs |
dc.subject | aritmetika pevného bodu | cs |
dc.title | Hardware-accelerated collision detection using bounded-error fixed-point arithmetic | en |
dc.type | článek | cs |
dc.type | article | en |
dc.rights.access | openAccess | en |
dc.type.version | publishedVersion | en |
dc.subject.translated | hardware-accelerated collision detection | en |
dc.subject.translated | graphic objects | en |
dc.subject.translated | fixed-point arithmetic | en |
dc.type.status | Peer-reviewed | en |
Vyskytuje se v kolekcích: | Number 1-3 (2006) |
Soubory připojené k záznamu:
Soubor | Popis | Velikost | Formát | |
---|---|---|---|---|
Raabe.pdf | 222,53 kB | Adobe PDF | Zobrazit/otevřít |
Použijte tento identifikátor k citaci nebo jako odkaz na tento záznam:
http://hdl.handle.net/11025/1356
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