Title: Performance of digital adder architectures in 180nm CMOS standard-cell technology
Authors: Pilato, Luca
Saponara, Sergio
Fanucci, Luca
Citation: 2016 International Conference on Applied Electronics: Pilsen, 6th – 7th September 2016, Czech Republic, p.211-214.
Issue Date: 2016
Publisher: Západočeská univerzita v Plzni
Document type: konferenční příspěvek
URI: http://hdl.handle.net/11025/35283
ISBN: 978–80–261–0601–2 (Print)
978–80–261–0602–9 (Online)
ISSN: 1803–7232 (Print)
1805–9597 (Online)
Keywords: sčítání;zpoždění;počítačová architektura;poptávka po energii;logická brána;technologie CMOS;teorie složitosti
Keywords in different language: adders;delays;computer architecture;power demand;logic gate;CMOS technology;complexity theory
Abstract in different language: In this paper, we present and compare the design and the performances of ten different implementations for a 16-bit adder in a 180nm CMOS standard-cell technology. Ripple carry adder, increment adder, triangle adder, uniform and progressive carry select adder, uniform and progressive carry bypass adder, conditional adder, ripple carry look ahead adder and hierarchical carry look ahead adder are taken into account. Every architecture is explained, highlighting the pros and cons. Finally, the results of area complexity, worst path timing and average power consumption for each implementation are shown.
Rights: © Západočeská univerzita v Plzni
Appears in Collections:Applied Electronics 2016
Applied Electronics 2016

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