Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Musala, Sarada | |
| dc.contributor.author | Srinivasulu, Avireni | |
| dc.contributor.editor | Pinker, Jiří | |
| dc.date.accessioned | 2019-10-09T05:54:41Z | |
| dc.date.available | 2019-10-09T05:54:41Z | |
| dc.date.issued | 2016 | |
| dc.identifier.citation | 2016 International Conference on Applied Electronics: Pilsen, 6th – 7th September 2016, Czech Republic, p.219-222. | en |
| dc.identifier.isbn | 978–80–261–0601–2 (Print) | |
| dc.identifier.isbn | 978–80–261–0602–9 (Online) | |
| dc.identifier.issn | 1803–7232 (Print) | |
| dc.identifier.issn | 1805–9597 (Online) | |
| dc.identifier.uri | http://hdl.handle.net/11025/35285 | |
| dc.format | 4 s. | cs |
| dc.format.mimetype | application/pdf | |
| dc.language.iso | en | en |
| dc.publisher | Západočeská univerzita v Plzni | cs |
| dc.rights | © Západočeská univerzita v Plzni | cs |
| dc.subject | FinFET | cs |
| dc.subject | logická brána | cs |
| dc.subject | střídače | cs |
| dc.subject | nízké napětí | cs |
| dc.subject | zpoždění | cs |
| dc.subject | simulace | cs |
| dc.title | FinFET based 4-BIT input XOR/XNOR logic circuit | en |
| dc.type | konferenční příspěvek | cs |
| dc.type | conferenceObject | en |
| dc.rights.access | openAccess | en |
| dc.type.version | publishedVersion | en |
| dc.description.abstract-translated | In this paper a structure for direct 4-BIT XOR/XNOR logic cell is proposed. This structure is proposed using pass transistor logic with FinFETs. This structure has less delay for the reason that its critical path consists of a minimum number of transistors. The basic advantage of this circuit is their symmetry in the logic. This design has a full voltage swing at the outputs and hence it has the good driving capability. The proposed design produces perfect outputs, even at low voltages and at high frequencies with the lesser transistor count. The proposed design is simulated using Cadence 20 nm FinFET technology at various supply voltages assorting from +0.6 V to +0.9 V. The simulation results illustrate that the proposed design has less delay and as well as less power consumption. | en |
| dc.subject.translated | FinFETs | en |
| dc.subject.translated | logic gate | en |
| dc.subject.translated | inverters | en |
| dc.subject.translated | low voltage | en |
| dc.subject.translated | delays | en |
| dc.subject.translated | simulation | en |
| dc.type.status | Peer-reviewed | en |
| Appears in Collections: | Applied Electronics 2016 Applied Electronics 2016 | |
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