Title: LHC Clock Conditioning Circuit for AFP Trigger Module
Authors: Georgiev, Vjačeslav
Zich, Jan
Citation: 2020 International Conference on Applied Electronics: Pilsen, 8th – 9h September 2020, Czech Republic.
Issue Date: 2020
Publisher: Západočeská univerzita v Plzni
Document type: conferenceObject
konferenční příspěvek
URI: http://hdl.handle.net/11025/39934
ISBN: 978-80-261-0891-7 (Print)
978-80-261-0892-4 (Online)
ISSN: 1803-7232 (Print)
1805-9597 (Online)
Keywords: CERN;zpožďovací linky;fyzika vysokých energií;LHC;urychlovač částic;klimatizace hodin;fyzické vybavení;synchronizace;radiační kalení
Keywords in different language: CERN;delay lines;high energy physics;LHC;particle accelerator;clock conditioning;physical instrumentation;synchronization;rad-hard
Abstract in different language: The timing and synchronisation of the detectors in particle physics play the key role due to the high event rates at particle accelerators. The trigger module in ATLAS Forward Physics project selects the events from time of flight detector belonging to the proton bunch. As the time position of the proton bunch is the same within each Large Hadron Collider period, from the clock conditioning circuit (CCC) can be derived the qualification signal for the trigger module input signals. The further processing of these events in trigger module is allowed by the CCC qualification. High speed delay line integrated circuits together with the logic gates and FPGA based controller were used for the realization of the CCC. This paper describes the design, construction and test procedure of the CCC.
Rights: © Západočeská univerzita v Plzni
Appears in Collections:Konferenční příspěvky / Conference Papers (KAE)
Applied Electronics 2020
Applied Electronics 2020

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