Full metadata record
| DC pole | Hodnota | Jazyk |
|---|---|---|
| dc.contributor.author | Georgiev, Vjačeslav | |
| dc.contributor.author | Zich, Jan | |
| dc.contributor.editor | Pinker, Jiří | |
| dc.date.accessioned | 2020-11-05T14:52:52Z | |
| dc.date.available | 2020-11-05T14:52:52Z | |
| dc.date.issued | 2020 | |
| dc.identifier.citation | 2020 International Conference on Applied Electronics: Pilsen, 8th – 9h September 2020, Czech Republic. | en |
| dc.identifier.isbn | 978-80-261-0891-7 (Print) | |
| dc.identifier.isbn | 978-80-261-0892-4 (Online) | |
| dc.identifier.issn | 1803-7232 (Print) | |
| dc.identifier.issn | 1805-9597 (Online) | |
| dc.identifier.uri | http://hdl.handle.net/11025/39934 | |
| dc.format | 4 s. | cs |
| dc.format.mimetype | application/pdf | |
| dc.language.iso | en | en |
| dc.publisher | Západočeská univerzita v Plzni | cs |
| dc.rights | © Západočeská univerzita v Plzni | cs |
| dc.subject | CERN | cs |
| dc.subject | zpožďovací linky | cs |
| dc.subject | fyzika vysokých energií | cs |
| dc.subject | LHC | cs |
| dc.subject | urychlovač částic | cs |
| dc.subject | klimatizace hodin | cs |
| dc.subject | fyzické vybavení | cs |
| dc.subject | synchronizace | cs |
| dc.subject | radiační kalení | cs |
| dc.title | LHC Clock Conditioning Circuit for AFP Trigger Module | en |
| dc.type | conferenceObject | en |
| dc.type | konferenční příspěvek | cs |
| dc.rights.access | openAccess | en |
| dc.type.version | publishedVersion | en |
| dc.description.abstract-translated | The timing and synchronisation of the detectors in particle physics play the key role due to the high event rates at particle accelerators. The trigger module in ATLAS Forward Physics project selects the events from time of flight detector belonging to the proton bunch. As the time position of the proton bunch is the same within each Large Hadron Collider period, from the clock conditioning circuit (CCC) can be derived the qualification signal for the trigger module input signals. The further processing of these events in trigger module is allowed by the CCC qualification. High speed delay line integrated circuits together with the logic gates and FPGA based controller were used for the realization of the CCC. This paper describes the design, construction and test procedure of the CCC. | en |
| dc.subject.translated | CERN | en |
| dc.subject.translated | delay lines | en |
| dc.subject.translated | high energy physics | en |
| dc.subject.translated | LHC | en |
| dc.subject.translated | particle accelerator | en |
| dc.subject.translated | clock conditioning | en |
| dc.subject.translated | physical instrumentation | en |
| dc.subject.translated | synchronization | en |
| dc.subject.translated | rad-hard | en |
| dc.type.status | Peer-reviewed | en |
| Vyskytuje se v kolekcích: | Konferenční příspěvky / Conference Papers (KAE) Applied Electronics 2020 Applied Electronics 2020 | |
Soubory připojené k záznamu:
| Soubor | Popis | Velikost | Formát | |
|---|---|---|---|---|
| 09232817.pdf | Plný text | 626,59 kB | Adobe PDF | Zobrazit/otevřít |
Použijte tento identifikátor k citaci nebo jako odkaz na tento záznam:
http://hdl.handle.net/11025/39934Všechny záznamy v DSpace jsou chráněny autorskými právy, všechna práva vyhrazena.