Title: New structures of 2n ± 1 modular adders for FPGAs
Authors: Younes, Dina
Šteffan, Pavel
Citation: Electroscope. 2011, č. 4, EDS 2011.
Issue Date: 2011
Publisher: Západočeská univerzita v Plzni, Fakulta elektrotechnická
Document type: konferenční příspěvek
ISSN: 1802-4564
Keywords: soustava zbytkových tříd;modulo 2n+1 sčítačky;programovatelná hradelná pole
Keywords in different language: residue number system;modulo 2n+1 adders;field programmable gate array
Abstract in different language: Two new structures of residue number system (RNS) adders for moduli 2n –1, 2n +1 are presented in this paper. The main idea is the utilization of the prefix computation technique in order to make the correction stage enclosed in the addition process instead of leaving it as the last stage of the modular addition. This provides faster and more efficient applications. Both designs allow efficient implementation on field programmable gate array (FPGA). Carry ripple adders (CRA) were utilized in the two structures due to the dedicated carry ripple logic built-in FPGAs. The proposed designs were implemented on Spartan-3 xc3s200-ft256-4 FPGA. A comparison with already published designs was done in terms of time and area consumption and showed significant time savings up to 44.7%.
Rights: Copyright © 2007-2010 Electroscope. All Rights Reserved.
Appears in Collections:Číslo 4 - EDS 2011 (2011)
Číslo 4 - EDS 2011 (2011)

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Please use this identifier to cite or link to this item: http://hdl.handle.net/11025/627

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