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DC poleHodnotaJazyk
dc.contributor.authorThanmai, T.
dc.contributor.authorRavindra, JVR
dc.contributor.editorPinker, Jiří
dc.date.accessioned2020-11-05T14:21:27Z
dc.date.available2020-11-05T14:21:27Z
dc.date.issued2020
dc.identifier.citation2020 International Conference on Applied Electronics: Pilsen, 8th – 9h September 2020, Czech Republic.en
dc.identifier.isbn978-80-261-0891-7 (Print)
dc.identifier.isbn978-80-261-0892-4 (Online)
dc.identifier.issn1803-7232 (Print)
dc.identifier.issn1805-9597 (Online)
dc.identifier.urihttp://hdl.handle.net/11025/39929
dc.format5 s.cs
dc.format.mimetypeapplication/pdf
dc.language.isoenen
dc.publisherZápadočeská univerzita v Plznics
dc.rights© Západočeská univerzita v Plznics
dc.subjectkryptografiecs
dc.subjectMontgomeryho multiplikátorcs
dc.subjectkompresorcs
dc.subjectFIR filtrcs
dc.titleHigh Performance, Low Power Architectureof 5-stage FIR Filter using ModifiedMontgomery Multiplieren
dc.typeconferenceObjecten
dc.typekonferenční příspěvekcs
dc.rights.accessopenAccessen
dc.type.versionpublishedVersionen
dc.description.abstract-translatedIn the field of VLSI, enhancement is promi-nent. Arithmetic circuits are one of the influential sectorsin today’s end products of electronics, where multipliersare one of the deciding factors of efficiency. Multiplierplays an important role in different applications suchas digital signal processing in which it acts as a keyhardware block. As time rolls down, the technologyexposed the ways for the initiation of many hardwareand software implementations of the faster multipliers.One among them is the Montgomery multiplier. Thefundamental operation in the Montgomery multiplier isthe modular multiplication. It is mainly used in FIRfilters, which in-turn has numerous applications suchas speech analysis, multi-rate signal processing, adaptivefilters, and averaging filters. With the usage of proposedcompressor in the conventional design of the multiplier,the number of transistor count has been declined by asignificant amount and made the design into an optimalarea design. This paper presents a modified Montgomerymultiplier design and its implementation in the5thorderFIR filter. The entire design simulation is carried outusing CMOS and PTL logic in 45 nm technology. Thereis an escalation in the result outcomes, and the multiplierhas an area efficiency of 65% and a power reduction ofabout 68% in comparison with conventional design.en
dc.subject.translatedcryptographyen
dc.subject.translatedMontgomery Multiplieren
dc.subject.translatedcompressoren
dc.subject.translatedFIR Filteren
dc.type.statusPeer-revieweden
Vyskytuje se v kolekcích:Applied Electronics 2020
Applied Electronics 2020

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