Title:	A 79μW 0.24mm28-channel neural signal recording front-end integrated circuit
Authors:	Rehman, Sami Ur Kamboh, Awais Yang, Yuning
Citation:	2017 International Conference on Applied Electronics: Pilsen, 5th – 6th September 2017, Czech Republic, p.183-186.
Issue Date:	2017
Publisher:	Západočeská univerzita v Plzni
Document type:	konferenční příspěvek conferenceObject
URI:	http://hdl.handle.net/11025/35436
ISBN:	978–80–261–0641–8 (Print) 978–80–261–0642–5 (Online)
ISSN:	1803–7232 (Print) 1805–9597 (Online)
Keywords:	nízký výkon;nervový záznam;protéza;SAR ADC;nervový zesilovač;SNR
Keywords in different language:	low power;neural recording;prosthesis;SAR ADC;neural amplifier;SNR
Abstract in different language:	This brief presents a new architecture for an ultra-low power and area-efficient 8-channel prototype of a neural signal recording front-end circuitry. For implantable neural recording circuits, low power and low area are two of the most critical requirements. In contrast to architectures existing in the literature, the presented recording path is centered on a single high-performance programmable gain-bandwidth amplifier, instead of employing a separate stand-alone amplifier for each electrode. The resulting circuitry requires smaller area and less power compared to all previously published designs. Implemented in 0.5μm CMOS and a supply voltage of 1.8V, the 8-channel recording path is measured to consume a total of 79μW of power and a net area of 0.24mm 2 . Therefore, allowing suitability of our design to be used in high channel count environments.
Rights:	© Západočeská univerzita v Plzni
Appears in Collections:	Applied Electronics 2017 Applied Electronics 2017

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