| Title: | Effective implementation methods of FIR filters in FPGAbased signal processing systems |
| Authors: | Korud, Andriy Korud, Vasyl |
| Citation: | CPEE – AMTEE 2013: Joint conference Computational Problems of Electrical Engineering and Advanced Methods of the Theory of Electrical Engineering: 4th – 6th September 2013 Roztoky u Křivoklátu, Czech Republic, p. II-3. |
| Issue Date: | 2013 |
| Publisher: | University of West Bohemia |
| Document type: | konferenční příspěvek conferenceObject |
| URI: | http://hdl.handle.net/11025/11569 |
| ISBN: | 978-80-261-0247-2 |
| Keywords: | programovatelná hradlová pole;FIR filtry |
| Keywords in different language: | field programmable gate array;FIR filters |
| Abstract: | Today’s modern FPGA devices and high speed digital to analog converters make it possible to use advanced direct synthesis technologies in semi-professional equipment. However this market segment is usually cost-sensitive, that’s why effective usage of available hardware resources is important. This paper analyzes implementation techniques of one of the most resourceconsuming building blocks – FIR filters, special attentions is paid to multiplierless approach. Proposed ways of improving existing methods using hardware resources available in the latest-generation FPGAs. |
| Rights: | © University of West Bohemia |
| Appears in Collections: | CPEE – AMTEE 2013 CPEE – AMTEE 2013 |
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